1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device with improved degree of integration and a reduced effect from parasitic resistances in the source and drain regions.
2. Description of the Related Art
FIGS. 12,13 and FIG. 14 show a semiconductor memory device of the past, FIG. 12 showing the upper interconnect layer, FIG. 13 showing the cross-section view thereof, and FIG. 14 showing the condition in which the above-noted upper interconnect layer is removed.
In the above-noted drawings, the reference numeral 101 denotes a p-channel source/drain region, 111 is a source region within the source/drain region 101, 112 is a drain region, and 113 is a gate. The upper layer aluminum interconnect 103a is connected to the source region 111 via a plurality of contacts 105. The upper layer interconnect 103b is connected to the drain region 112 via a plurality of contacts 115. However, as shown in FIG. 12, because of the existence of the interconnect 103c, which is provided on the same layer as the upper layer interconnects 103a and 103b, and which is provided so as to cross over the source region 111 and the drain region 112, there are cases in which it is possible to make contact between the source and drain regions and the upper layer interconnect over only approximately 50% or less of the total gate width W, and in such cases because the resistance value of the source and drain region diffusion layers is high, if the overall gate width W becomes large, the region 117 in the drawing, this being a transistor at the edge of the source/drain region, exhibits a significant loss of capacity as a transistor, leading to the problem of a loss of writing speed.
While a proposed semiconductor device with reduced influence from parasitic resistance in the drain region is disclosed in the Japanese Unexamined Patent Publication (KOKAI) No.62-89342, according to this disclosure a plurality of contacts are provided for the purpose of reducing the resistance value of the source or the drain, and a semiconductor integrated circuit is shown in which these contacts are connected by a wire having a small resistance value. Thus, the problem being solved and the constitution of this disclosure are not the same as the present invention.
Other examples of prior art include the Japanese Unexamined Patent Publication (KOKAI) No.8-70002, according to which a backed interconnect technology reduces the interconnect resistance, and the Japanese Unexamined Patent Publication (KOKAI) No.60-200541, according to which upper and lower polysilicon films are connected via a single contact hole, so as to increase the degree of integration. However, these disclosures are also different from the present invention in terms of problem to be solved and constitution.
Accordingly, it is an object of the present invention to improve on the above-noted drawbacks in the prior art, by providing a semiconductor memory device which reduces the influence of parasitic resistance in the source and drain regions, and increases the degree of integration.